1. Field of the Invention
The present disclosure relates to a method of forming a semiconductor device and to a semiconductor device. Particularly, the present disclosure relates to processing at the end of front-end-of-line (FEOL) fabrication.
2. Description of the Related Art
In modern electronic equipment, integrated circuits (ICs) experience a vast applicability in a continuously spreading range of applications. Particularly, the demand for increasing mobility of electronic devices at high performance and low energy consumption drives developments to more and more compact devices having features with sizes ranging even into the deep submicron regime; the more so as current semiconductor technologies are apt of producing structures with dimensions in the magnitude of 10 nm. With ICs representing a set of electronic circuit elements integrated on a semiconductor material, normally silicon, ICs can be made much smaller than discreet circuits composed of independent circuit components. The majority of present-day ICs are implemented by using a plurality of circuit elements, such as field effect transistors (FETs), also called metal oxide semiconductor field effect transistors (MOSFETs or simply MOS transistors), and passive elements, such as resistors and capacitors, integrated on a semiconductor substrate with a given surface area. Typically, present day integrated circuits involve millions of single circuit elements formed on a semiconductor substrate.
The basic function of a MOSFET is that of an electronic switching element, wherein a current through a channel region between two contact regions, referred to as source and drain, is controlled by a gate electrode to which a voltage relative to source and drain is applied. Particularly, in applying a voltage exceeding a characteristic voltage level to the gate electrode, the conductivity state of a MOSFET is changed and the characteristic voltage level, usually called “threshold voltage” and in the following referred to as Vt, characterizes the switching behavior of a MOSFET. In general, Vt depends nontrivially on the transistor's properties, e.g., materials, dimensions etc., such that the implementation of a desired Vt involves plural steps of adjustment and fine-tuning during the fabrication process.
Currently, the most common digital integrated circuits built today use CMOS logic, which is fast and offers a high circuit density and low power per gate. CMOS or “complementary symmetry metal oxide semiconductor,” as it is sometimes referred to, makes use of complementary and symmetrical pairs of P-type and N-type MOSFETs for implementing logic functions. Two important characteristics of CMOS devices are the high noise immunity and low static power consumption of a CMOS device because the series combination of complementary MOSFETs in a CMOS device draws significant power only momentarily during switching between ON- and OFF-states, since one transistor of a CMOS device is always in the OFF-state. Consequently, CMOS devices do not produce as much waste heat as other forms of logic, for example, transistor-transistor logic (TTL) or NMOS logic, which normally have some standing current even when not changing state.
With regard to FIGS. 1a and 1b, conventional FEOL processing after silicide formation is shown. FIG. 1a schematically illustrates in a cross-sectional view two gate structures 120 and 140 formed on a semiconductor substrate 100, conventionally a silicide substrate. In alignment with the gate structures 120, 140, source/drain regions 112, 114 and 116 are formed within the semiconductor substrate 100. Within the respective source/drain regions 112, 114 and 116, silicide regions 113, 115 and 117 are formed.
The gate structures 120 and 140 comprise respective gate dielectrics 124 and 144, respective gate electrode material layers 126 and 146, and respective sidewall spacers 128 and 148. The sidewall spacers 128 and 148 cover sidewalls of the respective gate electrode material layers 126 and 146. A respective one of silicide contacts 164 and 168 is formed during a preceding silicidation process on each of the gate electrode material layers 126 and 146.
Next, as illustrated in FIG. 1a, an etch process 170 is conventionally performed for removing the sidewall spacers 128, 148. As illustrated in FIG. 1b, the application of the etch process 170 removes the spacers 128, 148 after the silicide formation and before middle end-of-line processing, i.e., ILD layer deposition. Although the application of the process 170 increases a space between the two neighboring gate structures 120 and 140, the application of the process 170 results in a loss of active silicon and silicide material, as indicated in FIG. 1b by the broken lines S1, S2 and S3. Herein, each of the broken lines S1, S2 and S3 indicates a surface level of respective source/drain regions 112, 114, 116 and respective silicide regions 113, 115, 117 prior to the application of the process 170. The silicon recess and the corresponding silicide loss caused by process 170 poses the risk of causing ILD pinching during subsequent ILD-related process steps, such as TPEN deposition.
In spite of the effort to increase the space by removal of the sidewall spacers 128 and 148, the distance between the neighboring gate structures 120, 140, and particularly between the neighboring silicide regions 164 and 168, is decreased by a so-called “silicide overhang” 165 in case of silicide region 164 and a “silicide overhang” 169 in case of silicide region 168. Herein, a silicide overhang denotes that portion of a silicide region that extends beyond the sidewalls of the corresponding gate electrode material layer. Each of the silicide overhangs 165, 169 effectively lowers a minimum distance between the two neighboring gate structures 120, 140 by the amount of overhang, as indicated by reference numeral a. The minimum distance is denoted in FIG. 1b by reference numeral b. It is easy to see from FIG. 1b that the reduced distance b decreases the process margin for contact to gate shorts relating to contacts (not illustrated) contacting the respective ones of the silicide regions 113, 115 and 117.
In consequence, upon increasing the integration density of semiconductor devices on the semiconductor substrate 100, space between two neighboring gate structures 120 and 140 is reduced, leading to various problems, such as an unacceptably reduced process margin for contact to gate shorts and an increased parasitic capacitance between contacts and gate electrodes. Further issues arise with regard to the deposition of subsequent ILD layers, such as difficulties in depositing ILD layers without potential voids in the ILD layer due to the reduced distance b and resulting tungsten vias deteriorating device performance. Furthermore, due to the aggressive etch chemistry of the process 170 in FIG. 1a, a high silicon/silicide loss is created, causing further sub-optimal profiles for subsequent ILD layers, such that the problem of potential voids is increased rather than decreased.
In view of the above problems of the state in the art, it is, therefore, desirable to provide a method of forming a semiconductor device that overcomes the above-described drawbacks, as well as to provide a semiconductor device which does not suffer from the above flaws.